--
-- VHDL Architecture Fietssimulator_lib.s_prescaler.v
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp7985)
--          at - 16:25:02 31-05-2010
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_prescaler IS
  GENERIC( 
     n : NATURAL := 8
  );
  PORT( 
     clr  : IN     STD_LOGIC  := '0';
     cin  : IN     STD_LOGIC  := '1';
     clk  : IN     STD_LOGIC;
     rst  : IN     STD_LOGIC;
     q    : BUFFER INTEGER RANGE 0 TO n-1;
     cout : BUFFER STD_LOGIC
  );

END ENTITY s_prescaler;

--
ARCHITECTURE v OF s_prescaler IS

BEGIN 


 PROCESS(rst, clk)
   BEGIN
     IF rst = '1' THEN
       q <=  0;
     ELSIF RISING_EDGE(clk) THEN
       
       IF clr = '1' OR cout = '1' THEN
         q <= 0;
       ELSIF cin = '1' THEN
         q <= q + 1;
     END IF;    
       
     END IF;
   END PROCESS;
   
   
   cout <= cin WHEN q = n-1 ELSE '0'; 
   

 

  
  
END ARCHITECTURE v;

